CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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（2） Interval operation mode
In interval operation mode, high-speed internal oscillator clock frequency correction is performed
intermittently using timer interrupts, etc. The FCMD bit of the HOCOFC register is set to 1, which is
the interval Operation mode.
The FCST bit of the HOCOFC register is set to 1 when the high-speed internal oscillator clock
frequency correction Operation begins.
After the high-speed internal clock frequency correction action, the rising edge frequency counter
of the reference clock (fSUB/2 9) begins counting and stops counting on the rising edge of the next
reference clock (fSUB/2
9
). (frequency measurement phase).
The count value is then compared to the expected value and the correction value adjustment is
made as described below. (Frequency correction phase)
When the count value is greater than expected: the correction value is -1
The count value is more than expected hours: the correction value is +1
When the count value is within the expected range: the correction value is maintained
(high-speed internal clock frequency correction ends)
When the FCIE bit of the HOCOFC register is set to 1, a high-speed internal oscillator clock
frequency correction interrupt is generated after the high-speed internal oscillator clock frequency
correction is completed. In interval operation mode, the high-speed internal oscillator clock frequency
correction function repeats the frequency measurement stage and the frequency correction stage, and
stops the high-speed internal oscillator clock frequency correction function after the high-speed
internal oscillator clock frequency correction is completed.
Figure 4-22 is a timing diagram of the continuous operation mode.
Figure 4-22 Interval operation mode timing diagram
"0000000B"
"0000001B" "0000010B"
+１ +１
unchanged
Count value
retention
"0000010B"
Continuous action mode "1"
CRST clear: hardware clear when the correction value does not change.
Interrupt generation: when CRIE bit is 1, fHOCO pulse with
1 cycle width will be output when correction is completed.
Reference
clock
(fsub/2^9)
CRST
(Action enabling
position)
20 bit count
register
Correction
value
[6:0]
CRMD
(Action mode bit)
High speed internal
frequency correction
completion interrupt
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