CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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(4) Operation of single-count mode
(1) Enter the operating enabled state (TEmn=1) by writing 1 to the TSmn bit.
(2) The timer count register mn (TCRmn) holds the initial value until a start trigger signal is
generated.
(3) Detect the rising edge of TImn input.
(4) After the start trigger signal is generated, the value (m) of the TDRmn register is loaded into
the TCRmn register, and the count begins.
(5) When the TCRmn register decrements the count to 0000H, an INTTMmn interrupt is
generated, and the value of the TCRmn register becomes FFFFH, stopping the count.
.
Figure 5-29 Operation timing (single count mode)
Note: This is the timing when no noise filter is used. If a noise filter is used, edge detection is delayed by 2 more f
MCK
cycles
from the TImn input (3~4 cycles in total). The 1-cycle error is due to the fact that the TImn input is out of sync with the count
clock (f
MCK
).
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