CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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Figure 5-76 Example of register setting contents for multiple PWM output function
(slave channel) (when outputting 2 types of PWM)
(a) Timer mode registers mp, mq (TMRmp, TMRmq).
CKSmq1
1/0
CKSmq0
0
0
CCSmq
0
M/S
Note
0
STSmq2
1
STSmq1
0
STSmq0
0
CISmq1
0
CISmq0
0
0 0
MDmq3
1
MDmq2
0
MDmq1
0
MDmq0
1
14 13 12 11 10 9 8 7 6 5 4 3 2 1 015
TMRmq
operation mode of Channel p and q
100B:single counting mode
start trigger during operation
1: Trigger input valid.
start trigger selection
100B: Select master control channel INTTMmn
MASTERmp bit and MASTERmq bit configuration
(Channel 2) 0: slave channel
SPLITmp bit and SPLITmq bit configuration
(Channel 1, 3) 0: 16 bit Timer
Count clock selection
0: Select operational clock (fMCK)
operational clock (fMCK) selection
00B: select CKm0 as operational clock of Channel p and q
10B: select CKm1 as operational clock of Channel p and q
same as master control channel configuration
Timp and TImq Pin input edge selection
00B: set to "00B" since not used
CKSmp1
1/0
CKSmp0
0
0
CCSmp
0
M/S
Note
0
STSmp2
1
STSmp1
0
STSmp0
0
CISmp1
0
CISmp0
0
0 0
MDmp3
1
MDmp2
0
MDmp1
0
MDmp0
1
14 13 12 11 10 9 8 7 6 5 4 3 2 1 015
TMRmp
(b) Timer output register m (TOm).
0: Output 0 by TOmp and TOmq.
1: Output 1 by TOmp and TOmq.
(c) The timer output enable register m (TOEm).
0: Stop TOmp and TOmq outputs by counting runs.
1: Enable TOmp and TOmq outputs by counting runs.
(d) Timer output level register m (TOLm).
0: Positive logic output (active high).
1: Negative logic output (active-low).
(e) Timer outputs mode register m (TOMm).
1: Set slave channel output mode.
Note TMRm2: MASTERmp bit, MASTERmq bit
TMRm1, TMRm3: SPLITmp bit, SPLITmq bit
Remark m: unit number (m= 0,1) n: master channel number (n=0).
p: slave channel number q: slave channel number
n＜p＜ (p and q are integers greater than n)
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