Cmsemicon CMS32L051 - Page 272

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CMS32L051 User Manual |Chapter 11 A/D Converter
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Table 11-3 A/D conversion time (1/2)
(1) No A/D power stabilization wait time (software trigger mode/hardware trigger no wait mode).
A/D converter
mode register 0
(ADM0)
A/D sampling time
extension
register (ADSMPWAIT)
Convert
frequency of
clock ADCLK
(f
AD
)
12-bit resolution conversion time
Note 2
ADC conversion time = (number of sample clocks + number of
successive comparison clocks)/ fAD
FR2
FR1
FR0
ADSMPWAIT
Number of ADC conversion clocks
ADC conversion time
0
0
0
0
fCLK/32
16 ADCLK
(4 sample clocks +12 successive
comparison clocks).
16/ fAD
0
0
1
fCLK/16
0
1
0
fCLK/8
0
1
1
fCLK/4
1
0
0
fCLK/2
1
0
1
fCLK/1
0
0
0
1
fCLK/32
20 ADCLK
(8 sample clocks +12 successive
comparison clocks).
20/ fAD
0
0
1
fCLK/16
0
1
0
fCLK/8
0
1
1
fCLK/4
1
0
0
fCLK/2
1
0
1
fCLK/1
Note 1: To override the FR2~FR0 bits and ADSMPWAIT bits into different data, it must be done in the transition stop
state (ADCS=0).
Note 2. Time required for an ADC conversion = (number of sample clocks + number of successive comparison clocks)/
fAD
The number of sample clocks can be adjusted via the ADSMPWAIT register, which defaults to four ADCLK.
The fastest clock supported by ADCLK is 8MHz.
Note fCLK: The clock frequency of the CPU/peripheral hardware
fAD: The ADC converts the clock frequency up to 8MHz.