Cmsemicon CMS32L051 - Page 407

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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Figure 12-92 Flowchart of slave send and receive (single send and receive mode)
SSPI communication starts
configure transmit and receive
data
enable interrupt
write transmit data into
SIOp(=SDRmn[7:0])
wait for transmitting and reception
completes.
relevant initial configuration, refer to diagram 19-93
(select transmission completion interrupt)
regarding transmit and receive data, configure storage
region and data count (via software, any specified
internal RAM storage region, transmit data pointer
communnication data count)
after clear interrupt request flag(Ifxx) and
release interrupt mask(MKxx), enable
interrupt
start communication via clock
provided by master device.
SCI initial configuration
transmission completion interrupt
RETURN
transmit and receive next data?
disable interrupt (mask).
set STmn bit to 1.
communication completed.
No
Yes
main program
interrupt process program
main program
if interrupt generated via
transmission completion, jump to
interrupt process program.
update communication data count, confirm
whether there is next transmit and receive
data.
read transmit data from buffer and write into
SIOp, update transmit data pointer
Transmit and receive completed?
No
Yes
read received data into
SIOp(=SDRmn[7:0])
read receiving data and write into storage
region, update receive data pointer
Note Data must be sent to the SIOp register settings before the master device starts the output clock.
Remark m: Unit number (m=0) n: Channel number (n=0) p: SSPI number (p=00)