CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-31The operation of "(4) Data ~ Restart condition ~ Address" in Figure 14-31 is explained as
follows. After executing steps ⑦ and ⑧, execute <1> to <3>, and return to the data sending step in step
(3).
(7) At the end of the data transfer, an ACK is sent to the master via hardware because the slave's
ACKEn bit is "1." the master detects the ACK on the rising edge of the 9th clock (ACKDn=1).
(8) Both the master and slave enter a waiting state (SCLAn=0) on the falling edge of the 9th clock,
and both produce interrupts (INTIICAn: End of Transmission Interrupt).
<1> The slave reads the received data and releases the wait (WRELn=1).
<2> If the start condition is triggered again (STTn=1) on the master controller, the bus clock line rises
(SCLAn=1) and the bus data line drops (SDAAn=0) after the renewal start condition preparation
time ), generate a start condition (change SDAAn from 1 to 0 by SCLAn=1). Then, if a start
condition is detected, the bus clock line drops (SCLAn=0) after the hold time elapses, and the
communication is ready to be concluded.
<3> If the master writes the address +R/W (send) to the IICA shift register n (IICAn), the slave address
is sent.
Note n=0
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