Cmsemicon CMS32L051 - Page 561

V1.2.2
CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-32 Communication example of a slave device→master device
(Master device: select 8 clocks of waiting, slave device: select 9 clocks of waiting) (1/3)
(1) Start condition ~ address ~ data
slave address
AD0
AD1
AD2
AD3
AD4
AD5
AD6
master control
IICAn
ACKDn
（ACKdetection）
WTIMn
（8 or 9 clock cycles
waiting）
ACKEn
（ACK control）
MSTSn
（communicdat
ion state）
STTn
（ST trigger）
H
SPTn
（SP trigger）
L
WRELn
（release from
wait）
INTIICAn
（interrupt）
TRCn
（transmit
/reception）
bus
SCLAn(bus)
（Clock line）
SDAAn(bus)
（data line）
slave
IICAn
ACKDn
（ACKdetection）
STDn
（STdetection）
SPDn
（SPdetection
）
WTIMn
（8 or 9 clock cycles
waiting）
ACKEn
（ACK
control）
MSTSn
（communicdat
ion state）
WRELn
（release from
wait）
INTIICAn
（interrupt）
TRCn
（transmit
/reception）
H
H
L
note2
start
condition
D17





：slave device waits
：master device and slave device waits
ACK

note1
R
L
：master device waits
note3

Note 1. To release the master from waiting during reception, the IICAn must be set to "FFH" or the WRELn bit must be
set.
2. The time from the SDAAn pin signal drop to the SCLAn pin signal drop is at least 4.0us when set to standard
mode and at least 0.6us when set to fast mode.
3. To release the slave from waiting during transmission, you must write data to IICAn instead of setting the WRELn
bit.