CMS32L051 User Manual |Chapter 14 Serial interface IICA
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The descriptions of ① to ⑦ of "(1) Start condition ~ Address ~ Data" in Figure 14-32 are as follows:
(1) If the start condition is triggered by the master (STTn=1), the bus data line (SDAAn) drops, generating
a start condition (changing SDAAn from 1 to 0 by SCLAn=1 ). Thereafter, if a start condition is detected,
the master enters the master communication state (MSTSn=1), and the bus clock line drops (SCLAn=0) after
the hold time elapses, ending the communication readiness.
(2) If the master party writes the address +R (receive) to the IICA shift register n (IICAn), the slave
address is sent.
(3) On the slave, if the receiving address and the local station address (the value of SVAn) are the same,
the ACK is sent to the master controller through the hardware. The master detected ACK (ACKDn=1) on the
rising edge of the 9th clock.
(4) The master generates an interrupt on the falling edge of the 9th clock (INTIICAn: address send end
interrupt). A slave of the same address enters a waiting state (SCLAn=0) and generates an interrupt
(INTIICAn: Address Matching Interrupt)
Note
.
(5) The master changes the waiting timing to the 8th clock (WTIMn=0).
(6) The slave party writes the transmit data to the IICAn register to relieve the slave party of waiting.
(7) The master and controller release the wait (WRELn=1) and start the data transfer from the slave
device.
Note If the sending address and the slave address are different, the slave does not return an ACK (NACK: SDAAn=1)
to the master and does not generate an INTIICAn interrupt (address matching interrupt), nor does it enter a
waiting state.
However, the main controller generates an INTIICAn interrupt (address send end interrupt) for both ACK and
NACK.
Note 1. Figure 14-32 ①~⑲ shows a series of operation steps for data communication via the I2C bus.
Figure 14-32 (1) start condition ~ address ~ data describes steps (1) ~ (7).
Figure 14-32 (2) address ~ data ~ data illustrates steps (3) ~ (12).
Figure 14-32 (3) data ~ data ~ stop conditions shows steps (8) ~ (19).
2. n=0
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