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V1.2.2
CMS32L051 User Manual |Chapter 14 Serial interface IICA
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The description of ③ to ⑫ of "(2) Address - Data - Data" in Figure is as follows:
(3) On the slave side, if the receiving address and the local station address (the value of SVAn) are the
same, the ACK is sent to the master controller through the hardware. The master detected ACK (ACKDn=1)
on the rising edge of the 9th clock.
(4) The master generates an interrupt on the falling edge of the 9th clock (INTIICAn: address send end
interrupt). A slave of the same address enters a waiting state (SCLAn=0) and generates an interrupt
(INTIICAn: Address Matching Interrupt) note.
(5) The master changes the waiting timing to the 8th clock (WTIMn=0).
(6) The slave party writes the send data to the IICA shift register n (IICAn) to relieve the slave party of
waiting.
(7) The master releases the wait (WRELn=1) and start the data transfer from the slave device.
(8) The master enters a waiting state (SCLAn=0) on the falling edge of the 8th clock and generates an
interrupt (INTIICAn: Transmission end intermediate interruption). Because the ACKEn bit of the master
controller is 1, the ACK is sent to the slave through the hardware.
(9) The master reads the received data and releases the wait (WRELn=1).
(10) The slave detected an ACK (ACKDn=1) on the rising edge of the 9th clock.
(11) The slave enters the waiting state (SCLAn=0) on the falling edge of the 9th clock and generates an
interrupt (INTIICAn: transmit end interrupt).
(12) If the slave writes and sends data to the IICAn register, the slave is relieved of the wait and the data
transfer from the slave party to the main controller begins.
Note If the sending address and the slave address are different, the slave does not return an ACK (NACK: SDAAn=1)
to the master and does not generate an INTIICAn interrupt (address matching interrupt), nor does it enter a
waiting state.
However, the main controller generates an INTIICAn interrupt (address send end interrupt) for both ACK and
NACK.
Note 1. Figure 14-32 ①~⑲ shows a series of operation steps for data communication via the I2C bus.
Figure 16-32 (1) start condition ~ address ~ data describes steps (1) ~ (7).
Figure 16-32 (2) address ~ data ~ data describes steps (3) ~ (12).
Figure 16-32 (3) data ~ data ~ stop conditions shows steps (8) ~ (19).
2. n=0