USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1230/1328 RM0390 Rev 4
The core does not generate a separate interrupt when NAK or NYET is received by the
host functionality.
• Bulk and control IN transactions in DMA mode
The sequence of operations is as follows:
1. Initialize and enable the used channel (channel x) as explained in Section : Channel
initialization.
2. The OTG_HS host writes an IN request to the request queue as soon as the channel
receives the grant from the arbiter (arbitration is performed in a round-robin fashion).
3. The OTG_HS host starts writing the received data to the system memory as soon as
the last byte is received with no errors.
4. When the last packet is received, the OTG_HS host sets an internal flag to remove any
extra IN requests from the request queue.
5. The OTG_HS host flushes the extra requests.
6. The final request to disable channel x is written to the request queue. At this point,
channel 2 is internally masked for further arbitration.
7. The OTG_HS host generates the CHH interrupt as soon as the disable request comes
to the top of the queue.
8. In response to the CHH interrupt, de-allocate the channel for other transfers.
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