RM0390 Rev 4 165/1328
RM0390 Reset and clock control (RCC)
175
Bit 15 Reserved, must be kept at reset value.
Bits 14:6 PLLI2SN[8:0]: PLLI2S multiplication factor for VCO
These bits are set and cleared by software to control the multiplication factor of the VCO.
These bits can be written only when the PLLI2S is disabled. Only half-word and word
accesses are allowed to write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output
frequency is between 100 and 432 MHz.
VCO output frequency = VCO input frequency × PLLI2SN with 50 PLLI2SN 432
000000000: PLLI2SN = 0, wrong configuration
000000001: PLLI2SN = 1, wrong configuration ...
001100010: PLLI2SN = 50
...
001100011: PLLI2SN = 99
001100100: PLLI2SN = 100
001100101: PLLI2SN = 101
001100110: PLLI2SN = 102
...
110110000: PLLI2SN = 432
110110000: PLLI2SN = 433, wrong configuration ...
111111111: PLLI2SN = 511, wrong configuration
Note: Between 50 and 99 multiplication factors are possible for VCO input frequency higher
than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency
as specified above.
Bits 5:0 PLLI2SM[5:0]: Division factor for audio PLL (PLLI2S) input clock
Set and cleared by software to divide PLLI2S input clock before the VCO.
These bits can be written only when PLLI2S is disabled.
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.
VCO input frequency = PLL input clock frequency / PLLI2S with 2 PLLI2SM 63
000000: PLLI2SM = 0, wrong configuration
000001: PLLI2SM = 1, wrong configuration
000010: PLLI2SM = 2
000011: PLLI2SM = 3
000100: PLLI2SM = 4
...
111110: PLLI2SM = 62
111111: PLLI2SM = 63
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