ST STM32F446 Series User Manual

Contents RM0390
30/1328 RM0390 Rev 4
31.15.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 1118
31.15.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 1121
31.15.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 1124
31.15.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 1129
31.15.8 OTG receive status debug read/OTG status read and
pop registers (OTG_GRXSTSR/OTG_GRXSTSP) . . . . . . . . . . . . . . 1132
31.15.9 OTG receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 1135
31.15.10 OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
31.15.11 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
31.15.12 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 1137
31.15.13 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
31.15.14 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 1138
31.15.15 OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
31.15.16 OTG device IN endpoint transmit FIFO size register
(OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the
FIFO number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
31.15.17 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
31.15.18 OTG host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 1144
31.15.19 OTG host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 1145
31.15.20 OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
31.15.21 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
31.15.22 OTG host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 1147
31.15.23 OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
31.15.24 OTG host port control and status register (OTG_HPRT) . . . . . . . . . . 1149
31.15.25 OTG host channel x characteristics register (OTG_HCCHARx)
(x = 0..15[HS] / 11[FS], where x = Channel number) . . . . . . . . . . . . . 1151
31.15.26 OTG host channel x split control register (OTG_HCSPLTx)
(x = 0..15, where x = Channel number) . . . . . . . . . . . . . . . . . . . . . . . 1152
31.15.27 OTG host channel x interrupt register (OTG_HCINTx)
(x = 0..15[HS] / 11[FS], where x = Channel number) . . . . . . . . . . . . . 1153
31.15.28 OTG host channel x interrupt mask register (OTG_HCINTMSKx)
(x = 0..15[HS] / 11[FS], where x = Channel number) . . . . . . . . . . . . . 1155
31.15.29 OTG host channel x transfer size register (OTG_HCTSIZx)
(x = 0..15[HS] / 11[FS], where x = Channel number) . . . . . . . . . . . . . 1156

ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English