ST STM32F446 Series User Manual

RM0390 Rev 4 5/1328
RM0390 Contents
35
6.3.4 RCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.5 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 136
6.3.6 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 138
6.3.7 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 138
6.3.8 RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . 139
6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 142
6.3.10 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 144
6.3.11 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 145
6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 146
6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 146
6.3.14 RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 149
6.3.15 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.16 RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.17 RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.18 RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.19 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.20 RCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 159
6.3.21 RCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 161
6.3.22 RCC spread spectrum clock generation register (RCC_SSCGR) . . . . 162
6.3.23 RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 163
6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR) . . . . . . . . . . . . 166
6.3.25 RCC Dedicated Clock Configuration Register (RCC_DCKCFGR) . . . 167
6.3.26 RCC clocks gated enable register (CKGATENR) . . . . . . . . . . . . . . . . 169
6.3.27 RCC dedicated clocks configuration register 2 (DCKCFGR2) . . . . . . . 170
6.3.28 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.1 GPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.3.2 I/O pin multiplexer and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English