RM0390 Rev 4 581/1328
RM0390 General-purpose timers (TIM2 to TIM5)
581
Refer to Section 2.2.2: Memory map and register boundary addresses for the register
boundary addresses.
0x28
TIMx_PSC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PSC[15:0]
Reset value 0000000000000000
0x2C
TIMx_ARR
ARR[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
ARR[15:0]
Reset value 00000000000000000 0 0 0 000000000000
0x30 Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x34
TIMx_CCR1
CCR1[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
CCR1[15:0]
Reset value 00000000000000000 0 0 0 000000000000
0x38
TIMx_CCR2
CCR2[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
CCR2[15:0]
Reset value 00000000000000000 0 0 0 000000000000
0x3C
TIMx_CCR3
CCR3[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
CCR3[15:0]
Reset value 00000000000000000 0 0 0 000000000000
0x40
TIMx_CCR4
CCR4[31:16]
(TIM2 and TIM5 only, reserved on the other timers)
CCR4[15:0]
Reset value 00000000000000000 0 0 0 000000000000
0x44 Reserved
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x48
TIMx_DCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DBL[4:0]
Res.
Res.
Res.
DBA[4:0]
Reset value 00000 00000
0x4C
TIMx_DMAR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMAB[15:0]
Reset value 0000000000000000
0x50
TIM2_OR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ITR1_
RMP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value 00
0x50
TIM5_OR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IT4_
RMP
Res.
Res.
Res.
Res.
Res.
Res.
Reset value 00
Table 114. TIM2 to TIM5 register map and reset values (continued)
Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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