Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390
720/1328 RM0390 Rev 4
Master receiver
In the case of a read transfer, the RXNE flag is set after each byte reception, after the 8th
SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the FMPI2C_CR1
register. The flag is cleared when FMPI2C_RXDR is read.
If the total number of data bytes to be received is greater than 255, reload mode must be
selected by setting the RELOAD bit in the FMPI2C_CR2 register. In this case, when
NBYTES[7:0] data have been transferred, the TCR flag is set and the SCL line is stretched
low until NBYTES[7:0] is written to a non-zero value.
• When RELOAD=0 and NBYTES[7:0] data have been transferred:
– In automatic end mode (AUTOEND=1), a NACK and a STOP are automatically
sent after the last received byte.
– In software end mode (AUTOEND=0), a NACK is automatically sent after the last
received byte, the TC flag is set and the SCL line is stretched low in order to allow
software actions:
A RESTART condition can be requested by setting the START bit in the
FMPI2C_CR2 register with the proper slave address configuration, and number of
bytes to be transferred. Setting the START bit clears the TC flag and the START
condition, followed by slave address, are sent on the bus.
A STOP condition can be requested by setting the STOP bit in the FMPI2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.
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