RM0453 Rev 1 29/1461
RM0453 Contents
43
27.4 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
27.4.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . . 930
27.4.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . . 931
27.4.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . . 932
27.4.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . 933
27.4.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . . 934
27.4.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
27.4.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
27.4.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . 938
27.4.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . 940
27.4.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 941
27.4.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . . 941
27.4.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . . 942
27.4.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . . 942
27.4.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . . 943
27.4.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . . 945
27.4.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . . 946
27.4.17 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 947
27.4.18 TIM16 alternate function register 1 (TIM16_AF1) . . . . . . . . . . . . . . . . 947
27.4.19 TIM16 input selection register (TIM16_TISEL) . . . . . . . . . . . . . . . . . . 948
27.4.20 TIM17 option register 1 (TIM17_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . 948
27.4.21 TIM17 alternate function register 1 (TIM17_AF1) . . . . . . . . . . . . . . . . 949
27.4.22 TIM17 input selection register (TIM17_TISEL) . . . . . . . . . . . . . . . . . . 950
27.4.23 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
28 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
28.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
28.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
28.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
28.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
28.4.2 LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
28.4.3 LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
28.4.4 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
28.4.5 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
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