RM0453 Rev 1 339/1461
RM0453 Reset and clock control (RCC)
364
Bit 15 RFRST: Sub-GHz radio reset
This bit is set and cleared by software.
0: Sub-GHz radio software reset removed
1: Sub-GHz radio software reset active
Bit 14 RFRSTF: Sub-GHz radio in reset status flag
This bit is set and cleared by hardware.
0: Sub-GHz radio out of reset
1: Sub-GHz radio in reset
Bits 13:12 Reserved, must be kept at reset value.
Bits 11:8 MSISRANGE[3:0]: MSI clock ranges
These bits are configured by software and can be written only when MSIRGSEL = 1 in the
RCC_CR register. They are used to choose the MSI frequency range when exiting Standby
mode and when MSIRGSEL = 0.
0100: Range 4 around 1 MHz
0101: Range 5 around 2 MHz
0110: Range 6 around 4 MHz (reset value)
0111: Range 7 around 8 MHz
Others: Not allowed (hardware write protection)
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 LSIPRE: LSI frequency prescaler
This bit is set and cleared by software. It can be written at any time, however a new value is
only taken into account after a switching off and turning on sequence on LSI by using the
LSION bit.
0: LSI clock not divided (LSI)
1: LSI clock divided by 128 (LSI / 128)
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the
LSION bit is cleared, this bit goes low after three LSI clock cycles. This bit can be set even if
LSION = 0 if the LSI is requested by the CSS on LSE, by the independent watchdog or by
the RTC.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: LSI oscillator enable
This bit is set and cleared by software.
0: LSI oscillator off
1: LSI oscillator on
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