RM0453 Rev 1 41/1461
RM0453 Contents
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38.10.14 CPU1 ITM register map and reset values . . . . . . . . . . . . . . . . . . . . . 1406
38.11 CPU1 trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . 1407
38.11.1 TPIU supported port size register (TPIU_SSPSR) . . . . . . . . . . . . . . 1408
38.11.2 TPIU current port size register (TPIU_CSPSR) . . . . . . . . . . . . . . . . . 1408
38.11.3 TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . . . . 1409
38.11.4 TPIU selected pin protocol register (TPIU_SPPR) . . . . . . . . . . . . . . 1409
38.11.5 TPIU formatter and flush status register (TPIU_FFSR) . . . . . . . . . . . 1410
38.11.6 TPIU formatter and flush control register (TPIU_FFCR) . . . . . . . . . . 1410
38.11.7 TPIU formatter synchronization counter register (TPIU_FSCR) . . . . 1411
38.11.8 TPIU claim tag set register (TPIU_CLAIMSETR) . . . . . . . . . . . . . . . 1411
38.11.9 TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . . . . . . . . . . . . 1412
38.11.10 TPIU device configuration register (TPIU_DEVIDR) . . . . . . . . . . . . . 1412
38.11.11 TPIU device type identifier register (TPIU_DEVTYPER) . . . . . . . . . . 1413
38.11.12 TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . . . 1414
38.11.13 TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . . . 1414
38.11.14 TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . . . 1415
38.11.15 TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . . . 1415
38.11.16 TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . . . 1416
38.11.17 TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . . 1416
38.11.18 TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . . . 1417
38.11.19 TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . . 1417
38.11.20 TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . . 1418
38.11.21 CPU 1 TPIU register map and reset values . . . . . . . . . . . . . . . . . . . . 1418
38.12 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . 1420
38.12.1 DBGMCU identity code register (DBGMCU_IDCODER) . . . . . . . . . . 1420
38.12.2 DBGMCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . . . 1421
38.12.3 DBGMCU CPU1 APB1 peripheral freeze register 1
(DBGMCU_APB1FZR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422
38.12.4 DBGMCU CPU2 APB1 peripheral freeze register 1
(DBGMCU_C2APB1FZR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
38.12.5 DBGMCU CPU1 APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
38.12.6 DBGMCU CPU2 APB1 peripheral freeze register 2
(DBGMCU_C2APB1FZR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
38.12.7 DBGMCU CPU1 APB2 peripheral freeze register
(DBGMCU_APB2FZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
38.12.8 DBGMCU CPU2 APB2 peripheral freeze register
(DBGMCU_C2APB2FZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
38.12.9 DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . 1426
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