ST STM32WL5 Series User Manual

Contents RM0453
42/1461 RM0453 Rev 1
38.13 CPU2 ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427
38.13.1 CPU2 ROM1 memory type register (C2ROM1_MEMTYPER) . . . . . 1429
38.13.2 CPU2 ROM1 CoreSight peripheral identity register 4
(C2ROM1_PIDR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
38.13.3 CPU2 ROM1 CoreSight peripheral identity register 0
(C2ROM1_PIDR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
38.13.4 CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_PIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431
38.13.5 CPU2 ROM1 CoreSight peripheral identity register 2
(C2ROM1_PIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431
38.13.6 CPU2 ROM1 CoreSight peripheral identity register 3
(C2ROM1_PIDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432
38.13.7 CPU2 ROM1 CoreSight component identity register 0
(C2ROM1_CIDR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432
38.13.8 CPU2 ROM1 CoreSight peripheral identity register 1
(C2ROM1_CIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
38.13.9 CPU2 ROM1 CoreSight component identity register 2
(C2ROM1_CIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
38.13.10 CPU2 ROM1 CoreSight component identity register 3
(C2ROM1_CIDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
38.13.11 CPU2 ROM1 registers and reset values . . . . . . . . . . . . . . . . . . . . . . 1434
38.13.12 CPU2 ROM2 memory type register (C2ROM2_MEMTYPER) . . . . . 1435
38.13.13 CPU2 ROM2 CoreSight peripheral identity register 4
(C2ROM2_PIDR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435
38.13.14 CPU2 ROM2 CoreSight peripheral identity register 0
(C2ROM2_PIDR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
38.13.15 CPU2 ROM2 CoreSight peripheral identity register 1
(C2ROM2_PIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
38.13.16 CPU2 ROM2 CoreSight peripheral identity register 2
(C2ROM2_PIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
38.13.17 CPU2 ROM2 CoreSight peripheral identity register 3
(C2ROM2_PIDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1437
38.13.18 CPU2 ROM2 CoreSight component identity register 0
(C2ROM2_CIDR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
38.13.19 CPU2 ROM2 CoreSight peripheral identity register 1
(C2ROM2_CIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
38.13.20 CPU2 ROM2 CoreSight component identity register 2
(C2ROM2_CIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1438
38.13.21 CPU2 ROM2 CoreSight component identity register 3
(C2ROM2_CIDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
38.13.22 CPU2 ROM2 register map and reset values . . . . . . . . . . . . . . . . . . . 1439
38.14 CPU2 breakpoint unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English