Analog-to-digital converter (ADC) RM0453
578/1461 RM0453 Rev 1
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 102:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 71:
Data alignment and resolution (oversampling disabled: OVSE = 0) on page 552
0: Right alignment
1: Left alignment
Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this
ensures that no conversion is ongoing).
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Note: The software is allowed to write these bits only when ADEN = 0.
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