CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-31The descriptions of (7) to (15) of "(3) Data - Data - Stop condition" in Figure 14-31are as
follows:
⑦ At the end of the data transfer, the ACK is sent to the master controller through the hardware
because the ACKEn bit of the slave is 1. The master detected ACK (ACKDn=1) on the rising
edge of the 9th clock.
⑧ Both the master and slave enter a waiting state (SCLAn=0) on the falling edge of the 9th clock
and both generate interrupts (INTIICAn: End of Transmission Interrupt).
⑨ The master transmits data to the IICA shift register n (IICAn) to relieve the master from waiting.
⑩ If the slave reads the received data and releases the wait (WRELn=1), the master controller
begins to transmit the data to the slave.
⑪ At the end of the data transfer, the slave party (ACKEn=1) sends the ACK to the master
controller through the hardware. The master detected ACK (ACKDn=1) on the rising edge of the
9th clock.
⑫ Both the master and slave enter a waiting state (SCLAn=0) on the falling edge of the 9th clock
and both generate interrupts (INTIICAn: End of Transmission Interrupt).
⑬ The slave reads the received data and releases the wait (WRELn=1).
⑭ If the stop condition is triggered to assert (SPTn=1) in the master controller, the bus data line
(SDAAn=0) is cleared and the bus clock line is asserted (SCLAn=1), and the bus data line is
asserted (SDAAn=1) after the preparation time of the stop condition has passed. Generate a
stop condition (change SDAAn from 0 to 1 by SCLAn=1).
⑮ If a stop condition is generated, the slave detects the stop condition and generates an interrupt
(INTIICAn: Stop condition interrupt).
Note 1. Figure 14-31 ① to ⑮ shows a series of operational steps for data communication via the I
2
C bus.
Figure 14-31 (1) start condition ~ address ~ data describes steps (1) ~ (6).
Figure 14-31 (2) address ~ data ~ data illustrates steps (3) ~ (10).
Figure 14-31 (3) data ~ data ~ stop conditions illustrates steps (7) ~ (15)
2.n=0
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