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CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
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Table 4-3 Example of CPU transfering and SFR register setting (3/5)
(6) The CPU shifts from high-speed system clock operation (C) to high-speed internal oscillator clock
operation (B).
(Order of setting SFR registers).
The setting flag of the
SFR register
State transition
CSC registers
Oscillation accuracy is
stable waiting
CKC registers
HIOSTOP
MCM0
(C) (B)
0
1us
0
Not required in high-speed internal oscillator clock operation.
Note The oscillation accuracy of the high-speed internal oscillator clock is stable and waits to change due to temperature
conditions and during deep sleep mode.
(7) The CPU shifts from high-speed system clock operation (C) to subsystem clock operation (D).
(Order of setting SFR registers).
The setting flag of the
SFR register
State transition
CSC registers
Oscillation accuracy is
stable waiting
CKC registers
XTSTOP
CSS
(C) (D)
0
need
1
Not required in the operation of the secondary system clock.
(8) The CPU shifts from the subsystem clock operation (D) to the high-speed internal oscillator clock
operation (B).
(Order of setting SFR registers).
The setting flag of the
SFR register
State transition
CSC registers
Oscillation accuracy is
stable waiting
CKC registers
HIOSTOP
CSS
(D) (B)
0
1us
0
Not required in high-speed internal oscillator clock operation.
Note 1. Table 4-3 (A) ~ (I) correspond to Figure 4-17 (A) ~ (I).
2. The oscillation accuracy of the high-speed internal oscillator clock is stable and waits to change due to
temperature conditions and deep sleep mode.