Cmsemicon CMS32L051 - Page 95

V1.2.2
CMS32L051 User Manual |Chapter 4 Clock Generation Circuit
www.mcu.com.cn 95 / 703
Table 4-3 Example of CPU transfering and SFR register setting (4/5)
(9) The CPU shifts from subsystem clock operation (D) to high-speed system clock operation (C).
(Order of setting SFR registers).
The setting flag of the SFR register
State transition
OSTS
register
CSC registers
OSTC registers
CKC registers
MSTOP
CSS
(D) (C)
(X1Clock
X

concentrate
0
Confirmation is
required
0
(D) (C)
(X1Clock:10MHz＜f
X
)
concentrate
0
Confirmation is
required
0
(D) (C)
(External Master Clock)
concentrate
0
No confirmation is
required
0
Not required in high-speed system clock operation.
Note The following settings must be made for the oscillation settling time of the Oscillation Settling Time Selection
Register (OSTS).
 The expected oscillation stability time of the status register of the oscillation stability time counter (OSTC) ≤ the
oscillation stability time set by the OSTS register
Note that the clock must be set after the supply voltage reaches the set clock operable voltage (referring to the electrical
characteristics of the data sheet).
(10)
 (E) while the high-speed internal oscillator clock is running
(B).
 CPU transitions to sleep mode (F) while running at a high-speed system clock (C).
 The CPU is transferred to sleep mode (G) while the secondary system clock is running (D).
State transition
Set the content
(B) (s)
(C) (F)
(D) (G)
Execute the WFI instruction.
Remark: (A)~(I) in Table 4-3 correspond to (A)~(I) in Figure 4-17.