NXP Semiconductors PXN2020 - 31.3.2.8 eSCI LIN Control Register 2 (eSCI_LCR2); 31.3.2.9 eSCI LIN Transmit Register (eSCI_LTR)

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-15
31.3.2.8 eSCI LIN Control Register 2 (eSCI_LCR2)
This register provides the interrupt enable bits for the interrupt flags in Interrupt Flag and Status Register
2 (eSCI_IFSR2).
31.3.2.9 eSCI LIN Transmit Register (eSCI_LTR)
This register is used by the application to initiate the LIN frame header generation for both LIN TX frames
and LIN RX frames. If a LIN TX frame is generated, this register is used to provide the payload data for
the LIN TX frame.
If the application initiates a LIN TX frame transfer, i.e the TD bit is set to 1, the content and usage shown
in LIN Transmit Register (eSCI_LTR) — LIN TX Frame Generation applies (Figure 31-10). The initiation
and transmit of a TX frame is described in Section 31.4.6.3, LIN TX Frame Generation.
If the application initiates an LIN RX frame, i.e the TD bit is set to 0, the content and usage shown in LIN
Transmit Register (eSCI_LTR) — LIN RX Frame Generation applies (Figure 31-11). The initiation and
transmit of a RX frame is described in Section 31.4.6.4, LIN RX Frame Generation.
Each write access to this register increments the internal write access counter and enables the writing to
the next field. The write access counter is reset if:
• The LIN PE is in the idle state (eSCI_LCR1[LRES] = 1)
• A LIN TX frame was completely transmitted (eSCI_IFSR1[FRC] was set to 1)
• A LIN RX frame was completely received (eSCI_IFSR1[FRC] was set to 1)
• The module has entered halt mode.
Offset: ESCI_BASE + 0x000E Access: User read/write
0123456789101112131415
R000000
UQIE OFIE
00000000
W
Reset0000000000000000
Figure 31-9. eSCI LIN Control Register 2 (eSCI_LCR2)
Table 31-10. eSCI_LCR2 Field Descriptions
Field Description
UQIE Unrequested Data Received Interrupt Enable. This bit controls the eSCI_IFSR2[UREQ] interrupt request
generation.
0 UREQ interrupt request generation disabled.
1 UREQ interrupt request generation enabled.
OFIE Overflow Interrupt Enable. This bit controls the LINSTAT2[OVFL] interrupt request generation.
0 OVFL interrupt request generation disabled.
1 OVFL interrupt request generation enabled.