Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-31
Table 36-18 shows the data trace size encodings used for certain messages.
36.6.7 Nexus3+ Memory Map
This section describes the Nexus3+ programmer’s model. Nexus3+ registers are accessed using the
JTAG/OnCE port in compliance with IEEE 1149.1. See Section 36.6.9, Nexus3+ Register Access via
JTAG / OnCE for details on Nexus3+ register access.
NOTE
Nexus3+ registers and output signals are numbered using bit 0 as the least
significant bit. This bit ordering is consistent with the ordering defined by
the IEEE-ISTO 5001 standard.
Table 36-19 details the register map for the Nexus3+ module.
1110 Entry into a VLE page from a non-VLE page
1111 Entry into a non-VLE page from a VLE page
1
The device enters Low Power Mode when the Nexus stall mode is enabled
(Nexus3_DC1[OVC] = 0b011) and a trace message is in danger of over-flowing
the Nexus queue.
Table 36-18. Data Trace Size Encodings (TCODE = 5, 6, 13, 14)
DTM Size Encoding Transfer Size
000 Byte
001 Half-word (2 bytes)
010 Word (4 bytes)
011 Double-word (8 bytes)
100 String (3 bytes)
101–111 Reserved
Table 36-19. Nexus3+ Memory Map
Access
Opcode
Register Name Register Description Read Address Write Address
0x2 DC1 Development control 1 0x04 0x05
0x3 DC2 Development control 2 0x06 0x07
0x4 DS Development status 0x08 —
0x7 RWCS Read/write access control/status 0x0E 0x0F
0x9 RWA Read/write access address 0x12 0x13
0xA RWD Read/write access data 0x14 0x15
Table 36-17. Event Code Encoding (TCODE = 33)
Event Code Description
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