Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 12-3
12.1.2 Features
The flash memory module has these major features:
• Support for a 64-bit data bus for instruction fetch.
• Support for a 32-bit data bus for CPU loads and DMA access. Byte, halfword, word and
doubleword reads are supported. Only aligned word and doubleword writes are supported.
• Configurable read buffering and line prefetch support. Four line read buffers (128 bits wide) and a
prefetch controller are used to support single-cycle read responses for hits in the buffers.
• Hardware and software configurable read and write access protections on a per-master basis.
• Interface to the flash array controller is pipelined with a depth of 1, allowing overlapped accesses
to proceed in parallel for interleaved or pipelined flash array designs.
• Configurable access timing allowing use in a wide range of system frequencies.
• Multiple-mapping support and mapping-based block access timing (0-31 additional cycles)
allowing use for emulation of other memory types.
• Software programmable block program/erase restriction control for low, mid and high address
spaces.
• Erase of selected block(s).
• Read page size of 128 bits (4 words).
• ECC with single-bit correction, double-bit detection.
• Minimum program size is 2 consecutive 32 bit words, aligned on a 0-modulo-8 byte address, due
to ECC.
• Embedded hardware program and erase algorithm.
• Read While Write (RWW) with multiple partitions.
• Sleep mode for low power stand-by.
• Erase suspend, program suspend and erase-suspended program.
• Automotive flash which meets automotive endurance and reliability requirements.
• Shadow information stored in non-volatile shadow block.
• Independent program/erase of the shadow block.
12.1.3 Modes of Operation
12.1.3.1 Flash User Mode
User mode is the default operating mode of the flash module. In this mode, it is possible to read and write,
program and erase the flash module.
12.1.3.2 Sleep Mode
Sleep mode turns off most DC current sources within the module. The module is not accessible for read or
write once put to sleep.
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