NXP Semiconductors PXN2020 - 14.5 Bus Interface Unit (BIU)

e200z0 Core (Z0)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 14-13
14.5 Bus Interface Unit (BIU)
The BIU encompasses control and data signals supporting instruction and data transfers, support for
interrupts, including vectored interrupt logic, reset support, power management interface signals, debug
event signals, processor state information, Nexus /OnCE / JTAG interface signals, and a test interface.
The memory portion of the e200 core interface is comprised of a 32-bit wide system bus and a unified bus.
The memory interface supports read and write transfers of 8, 16, 24, and 32 bits, supports misaligned
transfers, and operates in a pipelined fashion.
Single-beat and misaligned transfers are supported for read and write cycles. Incrementing burst transfers
are supported for instruction prefetch operations.