Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-16 Freescale Semiconductor
bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEI[0]) provides a global set function, forcing the entire
contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes.
If bit 0 is set, the SEEI command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
24.3.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
The EDMA_CEEIR provides a memory-mapped mechanism to clear a given bit in the EDMA_EEIRL to
disable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEI[0]) provides a global clear function, forcing
the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of
this register return all zeroes.
If bit 0 is set, the CEEI command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDMA_BASE + 0x001A Access: User write-only
01234567
R
W NOP SEEI[0:6]
Reset00000000
Figure 24-8. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Table 24-9. EDMA_SEEIR Field Descriptions
Field Description
NOP No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
SEEI[0:6] Set Enable Error Interrupt.
0–31 Set corresponding bit in EDMA_EIRRL.
32–63 Reserved.
64–127 Set all bits in EDMA_EEIRL.
Note: Bits 2 and 3 (SEEIR[1:2]) are not used.
Offset: EDMA_BASE + 0x001B Access: User write-only
01234567
R
W NOP CEEI[0:6]
Reset00000000
Figure 24-9. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
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