Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-31
• The code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced
the MB (read the C/S word and then unlocked the MB)
If the first MB with a matching ID is not free to receive the new frame, then the matching algorithm keeps
looking for another free MB until it finds one. If it cannot find one that is free, then it overwrites the last
matching MB (unless it is locked) and sets the code field to OVERRUN (refer to Table 29-4 and
Table 29-5). If the last matching MB is locked, then the new message remains in the SMB, waiting for the
MB to be unlocked (see Section 29.4.5.3, Message Buffer Lock Mechanism).
Suppose, for example, that the FIFO is disabled and there are two MBs with the same ID, and FlexCAN
starts receiving messages with that ID. Let us say that these MBs are the second and the fifth in the array.
When the first message arrives, the matching algorithm finds the first match in MB number 2. The code
of this MB is EMPTY, so the message is stored there. When the second message arrives, the matching
algorithm finds MB number 2 again, but it is not free to receive, so it keeps looking and finds MB number
5 and stores the message there. If yet another message with the same ID arrives, the matching algorithm
finds out that there are no matching MBs that are free to receive, so it decides to overwrite the last matched
MB, which is number 5. In doing so, it sets the code field of the MB to indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a reception queue
(in addition to the full featured FIFO) to allow more time for the CPU to service the MBs. By programming
more than one MB with the same ID, received messages are queued into the MBs. The CPU can examine
the time stamp field of the MBs to determine the order in which the messages arrived.
The matching algorithm described above can be changed to be the same one used in previous versions of
the FlexCAN module. When the BCC bit in CANx_MCR is negated, the matching algorithm stops at the
first MB with a matching ID that it founds, whether this MB is free or not. As a result, the message
queueing feature does not work if the BCC bit is negated.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports individual
masking per MB. Please refer to Section 29.3.4.11, Rx Individual Mask Registers (CANx_RXIMR0 –
CANx_RXIMR63). During the matching algorithm, if a mask bit is asserted, then the corresponding ID
bit is compared. If the mask bit is negated, the corresponding ID bit is “don’t care”. Please note that the
individual mask registers are implemented in RAM, so they are not initialized out of reset. Also, they can
only be programmed if the BCC bit is asserted and while the module is in freeze mode.
FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK,
CANx_RX14MASK, and CANx_RX15MASK) for backwards compatibility. This alternate masking
scheme is enabled when the BCC bit in the CANx_MCR Register is negated.
29.4.5 Data Coherence
To maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described in
Section 29.4.1, Transmit Process, and Section 29.4.3, Receive Process. Any form of CPU accessing an
MB structure within FlexCAN other than those specified may cause FlexCAN to behave in an
unpredictable way.
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