Error Correction Status Module (ECSM)
PXN20 Microcontroller Reference Manual, Rev. 1
19-10 Freescale Semiconductor
19.2.2.6 Platform Flash ECC Master Number Register (PFEMR)
The PFEMR is a 4-bit register for capturing the AXBS bus master number of the last properly enabled
ECC event in the platform flash memory. Depending on the state of the ECC configuration register, an
ECC event in the platform flash causes the address, attributes and data associated with the access to be
loaded into the PFEAR, PFEMR, PFEAT, and PFEDR registers and also the appropriate flag (PF1BC or
PFNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 19-6 and Table 19-8 for the platform
flash ECC master number register definition.
19.2.2.7 Platform Flash ECC Attributes Register (PFEAT)
The PFEAT is an 8-bit register for capturing the AXBS bus master attributes of the last properly enabled
ECC event in the platform flash memory. Depending on the state of the ECC configuration register, an
Offset: ECSM_BASE_ADDR + 0x0050 Access: User read-only
0 123456789101112131415
R PFEAR
W
ResetU UUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PFEAR
W
ResetU UUUUUUUUUUUUUUU
Figure 19-5. Platform Flash ECC Address (PFEAR) Register
Table 19-7. PFEAR Field Descriptions
Field Description
PFEAR Platform Flash ECC Address Register. Contains the faulting access address of the last properly enabled platform
flash ECC event.
Offset: ECSM_BASE_ADDR + 0x0056 Access: User read-only
01234567
R0 0 0 0 PFEMR
W
Reset 0 0 0 0 U U U U
Figure 19-6. Platform Flash ECC Master Number (PFEMR) Register
Table 19-8. PFEMR Field Descriptions
Field Description
PFEMR Platform Flash CC Master Number Register. Contains the AXBS bus master number of the faulting access of the
last properly enabled platform flash ECC event.
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