NXP Semiconductors PXN2020 - 29.3.2 Message Buffer Structure

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-7
One of the following actions be taken to avoid the above problems:
• Do not enable the RxFIFO. If CANx_MCR[FEN]=0 then the Rx FIFO
is disabled and thus the masks RXGMASK, RX14MASK and
RX15MASK do not affect it.
• Enable Rx Individual Mask Registers. If the Backwards Compatibility
Configuration bit in the FlexCAN Module Configuration Register
(CANx_MCR[BCC], bit 15) is set then the Rx Individual Mask
Registers (RXIMR0-63) are enabled and thus the masks RXGMASK,
RX14MASK and RX15MASK are not used.
• Do not use masks RXGMASK, RX14MASK and RX15MASK (rather
set them to reset value, which is 0xffff_ffff) when CANx_MCR[FEN]=1
and CANx_MCR[BCC]=0. In this case, filtering processes for both Rx
MBs and Rx FIFO are not affected by those masks.
• Do not configure any MB as Rx (i.e. let all MBs as either Tx or inactive)
when CANx_MCR[FEN]=1 and CANx_MCR[BCC]=0. In this case,
the masks RXGMASK, RX14MASK and RX15MASK can be used to
affect ID Tables without affecting filtering process for Rx MBs.
29.3.2 Message Buffer Structure
The message buffer structure used by the FlexCAN module is represented in Figure 29-2. Both extended
and standard frames (29-bit identifier and 11-bit identifier, respectively) used in the CAN specification
(version 2.0 Part B) are represented.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0x0
CODE
SRR
IDE
RTR
LENGTH TIME STAMP
0x4 PRIO ID (Extended/Standard) ID (Extended)
0x8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3
0xC Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
Figure 29-2. Message Buffer Structure
Table 29-3. Message Buffer Field Descriptions
Name Description
CODE Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module
itself, as part of the message buffer matching and arbitration process. The encoding is shown in Ta ble 2 9-4
and Ta bl e 29 -5. See Section 29.4, Functional Description, for additional information.
SRR Substitute Remote Request. Fixed recessive bit, used only in extended format. It must be set to 1 by the user
for transmission (Tx Buffers) and is stored with the value received on the CAN bus for Rx receiving buffers. It
can be received as either recessive or dominant. If FlexCAN receives this bit as dominant, then it is interpreted
as arbitration loss.
0 Dominant is not a valid value for transmission in extended format frames.
1 Recessive value is compulsory for transmission in extended format frames.