NXP Semiconductors PXN2020 - 34.3.2.33 Decode Signals Delay Register (DSDR)

Analog-to-Digital Converter (ADC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 34-37
34.3.2.33 Decode Signals Delay Register (DSDR)
The DSDR register specifies the delay between the external decode signals and the start of the sampling
phase.
Address: Base + 0x00EC Access: User read/write
0123456789101112131415
R000000000000000OFF
SET
LOAD
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000
OFFSET_WORD
W
Reset0000000000000000
Figure 34-33. Offset Word Register (OFFWR)
Table 34-35. OFFWR Field Descriptions
Field Description
OFFSETLOAD Used to enable offset loading. This bit should be written before writing the OFFSET_WORD field.
OFFSET_
WORD
The offset word coefficient generated at the end of the offset cancellation phase is latched into this register.
That offset word can be also written by software. In that case, it is loaded into the analog ADC and used as the
offset cancellation word instead of the one calculated using the offset cancellation process. That field should
be written before starting conversion.
Address: ADC_ Base + 0x00C4 Access: User read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000
DSD
W
Reset0000000000000000
Figure 34-34. Decode Signals Delay Register (DSDR)
Table 34-36. DSDR Field Descriptions
Field Description
DSD The delay between the external decode signals and the start of the sampling phase. It is used to take into
account the settling time of the external mux.