NXP Semiconductors PXN2020 - 4.4.1 Reset Configuration Timing

Resets
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 4-5
4.4.1 Reset Configuration Timing
The timing diagram in Figure 4-1 shows the sampling of the BOOTCFG (PK9) pin for a power-on reset.
The timing diagram is also valid for internal/external resets assuming V
DD
and V
DD33
are within valid
operating ranges. The value of the BOOTCFG pin is latched 4 clock cycles before the negation of the
RESET
pin and stored in the reset status register.
Figure 4-1. Reset Configuration Timing
RESET
V
DD
POR
BOOTCFG is latched.
(4 clock cycles)
1000
1
clocks
BOOTCFG can be applied,
but not latched.
1
If the CRP_RECPTR[FASTREC] is set, then the clock count is 16 for Sleep mode recovery.
User drives
configuration pins
relative to RESET
Internal
Reset