Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 1-7
• Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit general
purpose registers
• Floating point
—IEEE
®
754 compatible with software wrapper
— Single precision in hardware; double precision with software library
— Conversion instructions between single precision floating point and fixed point
• Wait instruction
• Extensive system development support through Nexus debug module
1.7.2 I/O Processor High Performance e200z0 Core (IOP)
The IOP supports the following features:
• High performance, low cost e200z0 core processor for managing peripherals and interrupts
• Single issue 4-stage pipelined in-order execution, 32-bit Power Architecture
®
CPU
• Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
— Results in efficient code size footprint
— Minimizes impact on performance
• Branch processing acceleration using lookahead instruction buffer
• Load/store unit
— 1-cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
• Thirty-two 32-bit general purpose registers (GPRs)
• Hardware vectored interrupt support
• Reservation instructions for implementing read-modify-write constructs
• Multi-cycle divide (divw) and load multiple (lmw) store multiple (smw) multiple class
instructions, can be interrupted to prevent increases in interrupt latency
• Extensive system development support through Nexus debug port
1.7.3 On-Chip Flash
On-chip flash on the PXN20 devices features the following:
• 2 MB burst flash memory
— Flash partitioning: 4 16 KB; 4 16 KB; 2 64 KB; 2 128 KB; 6 256 KB
— 16 KB shadow flash blocks
— Typical flash access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at
116 MHz
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
• Dual flash ports to minimize access contention between main core and IOP
To Next Page
Loading...
