Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-60 Freescale Semiconductor
10. Enable DMA channel by enabling the DMA enable request for the DMA channel assigned to the
DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
30.5.2 Baud Rate Settings
Table 30-35 shows the baud rate that is generated based on the combination of the baud rate prescaler PBR
and the baud rate scaler BR in the DSPI_CTARn registers. The values calculated assume a 100 MHz
system frequency and the double baud rate DBR bit is clear.
30.5.3 Delay Settings
Table 30-36 shows the values for the Delay after Transfer (T
DT
) and CS to SCK Delay (T
CSC
) that can be
generated based on the prescaler values and the scaler values set in the DSPI_CTARn registers. The values
calculated assume a 100 MHz system frequency. This table does not apply for TSB continuous mode.
Table 30-35. Baud Rate Values
Baud Rate Divider Prescaler Values
2357
Baud Rate Scaler Values
2 25.0M 16.7M 10.0M 7.14M
4 12.5M 8.33M 5.00M 3.57M
6 8.33M 5.56M 3.33M 2.38M
8 6.25M 4.17M 2.50M 1.79M
16 3.12M 2.08M 1.25M 893k
32 1.56M 1.04M 625k 446k
64 781k 521k 312k 223k
128 391k 260k 156k 112k
256 195k 130k 78.1k 55.8k
512 97.7k 65.1k 39.1k 27.9k
1024 48.8k 32.6k 19.5k 14.0k
2048 24.4k 16.3k 9.77k 6.98k
4096 12.2k 8.14k 4.88k 3.49k
8192 6.10k 4.07k 2.44k 1.74k
16384 3.05k 2.04k 1.22k 872
32768 1.53k 1.02k 610 436
To Next Page
Loading...
