Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-5
30.1.4.4 Halt Mode
Halt mode is used for MCU power management and controlled by the individual HLT bits in the
SIU_HLT0 register. When a request is made to enter halt mode (assert HLT bit), the DSPI block
acknowledges the request and completes the transfer in progress. When the DSPI reaches the frame
boundary it signals that the system clocks to the DSPI block may be shut off.
30.1.4.5 Debug Mode
Debug mode is used for system development and debugging. If the device enters debug mode while the
FRZ bit in the DSPI_MCR is set, the DSPI stops all serial transfers. If the device enters debug mode while
the FRZ bit is negated, the DSPI behavior is unaffected and remains dictated by the block-specific mode
and configuration of the DSPI.
30.2 External Signal Description
The DSPI supports the following external signals:
Refer to Table 3-1 and Section 3.4, Detailed Signal Description, for detailed signal descriptions.
30.3 Memory Map and Registers
This section provides a detailed description of all DSPI registers.
30.3.1 Module Memory Map
The DSPI memory map is shown in Table 30-2 (the memory map is the same for each individual DSPI
module). The address of each register is given as an offset to the DSPI base address. Registers are listed
in address order, identified by complete name and mnemonic, and list the type of accesses allowed.
Table 30-1. External Signals
Name I/O Type
Function
Master Mode Slave Mode
PCS[0] / SS
Output / Input Peripheral Chip Select 0 Slave Select
PCS[1] – PCS[4] Output Peripheral Chip Select 1–4 unused
PCS[5] / PCSS
Output Peripheral Chip Select 5 / Peripheral
Chip Select Strobe
unused
SIN Input Serial Data In
SOUT Output Serial Data Out
SCK Output / Input Serial Clock (output) Serial Clock (input)
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