NXP Semiconductors PXN2020 - 30.5.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO; 30.5.5.2 Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-63
30.5.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX
FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following equation:
Eqn. 30-10
The memory address of the last-in entry in the TX FIFO is computed by the following equation:
Eqn. 30-11
where:
TX FIFO base: base address of TX FIFO
TXCTR: TX FIFO counter
TXNXTPTR: transmit next pointer
TX FIFO depth: transmit FIFO depth
30.5.5.2 Address Calculation for the First-in Entry and Last-in Entry in the RX
FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following equation:
Eqn. 30-12
The memory address of the last-in entry in the RX FIFO is computed by the following equation:
Eqn. 30-13
where:
RX FIFO base: base address of RX FIFO
RXCTR: RX FIFO counter
POPNXTPTR: pop next pointer
RX FIFO depth: receive FIFO depth
First-in Entry Address TX FIFO Base 4 TXNXTPTR+=
Last-in Entry address TX FIFO Base 4 modulo TX FIFO depth TXCTR TXNXTPTR 1–++=
First-in Entry Address RX FIFO Base 4 POPNXTPTR+=
Last-in Entry address RX FIFO Base 4 modulo RX FIFO depth RXCTR POPNXTPTR 1–++=