PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 1-1
Chapter 1
Introduction
1.1 Overview
The PXN20 products are compatible 32-bit microcontrollers built on Power Architecture
®
technology.
This document describes the available features, and highlights important characteristics of the devices.
The PXN20 products are designed to address the need for single chip industrial networking applications
and are tailored to address the need for high performance and high memory size while keeping the power
consumption low. Their core and bus architecture offer high performance processing optimized for
managing intensive data exchanges between different types of communication protocols. It capitalizes on
the available development infrastructure of current Power Architecture devices and will be supported with
software drivers and an operating system to assist with user implementations.
The PXN20 devices have two levels of memory hierarchy, a 32 KB unified cache, and 2 MB of internal
flash. The PXN20 has 128 KB on-chip L2 SRAM and the PXN21 has 592 KB on-chip L2 SRAM. Refer
to Table 1 for specific memory and feature sets of the family members.
1.2 PXN20 Features
Table 1-1 provides a summary of the different members of the PXN20 family and their features. This
information is intended to provide an understanding of the range of functionality offered by this family of
devices.
Table 1-1. PXN20 Family Feature Set
Feature PXN20 PXN21
Central Processing Unit (CPU) e200z650 e200z650
Cache 32K, 4/8way 32K, 4/8way
Floating Point Unit (FPU) Yes Yes
Signal Processing Engine (SPE) Yes Yes
Memory Management Unit (MMU) 32 entry 32 entry
CPU Execution Speed Static, 116 MHz Static, 116 MHz
Input/Output Processor (IOP) e200z0 e200z0
IOP Execution Speed 1/2 CPU execution speed 1/2 CPU execution speed
Flash with ECC 2 MB 2 MB
Data Flash Block 8x16 KB 8x16 KB
RAM with ECC 592 KB 128 KB
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