NXP Semiconductors PXN2020 - 24.3.2.16 eDMA Channel n Priority Registers (EDMA

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Enhanced Direct Memory Access Controller (eDMA)

PXN20 Microcontroller Reference Manual, Rev. 1

24-22 Freescale Semiconductor

Figure 24-16. EDMA Hardware Request Status Register Low (EDMA_HRSL)

24.3.2.16 eDMA Channel n Priority Registers (EDMA_CPRn)

When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of

these registers define the unique priorities associated with each channel. The channel priorities are

evaluated by numeric value; that is, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. If

software modifies channel priority values, then the software must ensure that the channel priorities contain

unique values. Otherwise, a configuration error is reported. The range of the priority value is limited to the

values of 0 through 31. When read, the GRPPRI bits of the EDMA_CPRn register reflect the current

priority level of the group of channels in which the corresponding channel resides. GRPPRI bits are not

affected by writes to the EDMA_CPRn registers. The group priority is assigned in the EDMA_CR. See

Figure 24-2 and Table 24-3 for the EDMA_CR definition.

Channel preemption is enabled on a per-channel basis by setting the ECP bit in the EDMA_CPRn register.

Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of

starting a higher priority channel. After the preempting channel has completed all its minor loop data

transfers, the preempted channel is restored and resumes execution. After the restored channel completes

one read/write sequence, it is again eligible for preemption. If any higher priority channel requests service,

the restored channel is suspended and the higher priority channel is serviced. Nested preemption

(attempting to preempt a preempting channel) is not supported. After a preempting channel begins

execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected for both

group and channel arbitration modes.

Address: EDMA_BASE + 0x0034 Access: User read/write

0123456789101112131415

HRS

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

HRS

Reset0000000000000000

Table 24-17. EDMA_HRSL Field Descriptions

Field Description

HRSn DMA Hardware Request Status

0 A hardware service request for channel n is not present.

1 A hardware service request for channel n is present.

Note: The hardware request status reflects the state of the request as seen by the arbitration logic. Therefore,

this status is affected by the EDMA_ERQRL[ERQn] bit.

NXP Semiconductors PXN2020 - 24.3.2.16 eDMA Channel n Priority Registers (EDMA_CPRn)