NXP Semiconductors PXN2020 - 25.3.4.17 Descriptor Group Upper Address (GAUR)

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-24 Freescale Semiconductor
25.3.4.17 Descriptor Group Upper Address (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table used in
the address recognition process for receive frames with a multicast address. This register must be
initialized by the user.
Offset: FEC_BASE + 0x011C Access: User read/write
0123456789101112131415
R
IADDR2
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IADDR2
W
ResetUUUUUUUUUUUUUUUU
Figure 25-17. Descriptor Individual Lower Address (IALR)
Table 25-19. IALR Field Descriptions
Field Description
IADDR2 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a
unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
Offset: FEC_BASE + 0x0120 Access: User read/write
0123456789101112131415
R
GADDR1
W
ResetUUUUUUUUUUUUUUUU
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
GADDR1
W
ResetUUUUUUUUUUUUUUUU
Figure 25-18. Descriptor Group Upper Address Register (GAUR)