NXP Semiconductors PXN2020 - 30.3.2.3 DSPI Clock and Transfer Attributes Registers 0-7 (DSPI_CTARn)

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-10 Freescale Semiconductor
30.3.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn)
The DSPI_CTARn registers are used to define different transfer attribute configurations. SPI and DSI
transfers select one of the DSPI_CTARn registers from which to get their transfer attributes. The user must
not write to the DSPI_CTARn registers while the DSPI is in the running state.
In master mode, the DSPI_CTARn registers define combinations of transfer attributes such as frame size,
clock phase and polarity, data bit ordering, baud rate, and various delays. In slave mode, a subset of the
bitfields in the DSPI_CTAR0 and DSPI_CTAR1 registers are used to set the slave transfer attributes. See
the individual bit descriptions for details on which bits are used in slave modes.
When the DSPI is configured as a SPI master, the CTAS field in the command portion of the TX FIFO
entry selects which DSPI_CTARn register is used. When the DSPI is configured as a SPI bus slave, the
DSPI_CTAR0 register is used.
When the DSPI is configured as a DSI master, the DSICTAS field in the DSPI DSI Configuration Register
(DSPI_DSICR) selects which DSPI_CTARn register is used. For more information on the DSPI_DSICR,
see Section 30.3.2.10, DSPI DSI Configuration Register (DSPI_DSICR). When the DSPI is configured as
a DSI bus slave, the DSPI_CTAR1 register is used.
In CSI configuration, the transfer attributes are selected based on whether the current frame is SPI data or
DSI data. SPI transfers in CSI configuration follow the protocol described for SPI configuration, and DSI
transfers in CSI configuration follow the protocol described for DSI configuration. CSI configuration is
only valid in conjunction with master mode. See Section 30.4.5, Combined Serial Interface (CSI)
Configuration, for more details.
Offset: DSPI_BASE + 0x0008 Access: User read/write
0123456789101112131415
R
SPI_TCNT
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Figure 30-4. DSPI Transfer Count Register (DSPI_TCR)
Table 30-4. DSPI_TCR Field Descriptions
Field Description
SPI_TCNT SPI Transfer Counter. SPI_TCNT is used to keep track of the number of SPI transfers made. The SPI_TCNT field
counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is incremented every time the last bit of
a SPI frame is transmitted. A value written to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to
0 at the beginning of the frame when the CTCNT field is set in the executing SPI command. The transfer counter
wraps around; i.e., incrementing the counter past 65,535 (0xFFFF) resets the counter to 0.