Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
33-10 Freescale Semiconductor
• First level of arbitration is done between all events associated to one counter. The lowest index
channel has the highest priority.
• Second level of arbitration is done between counters. The lowest index counter has the highest
priority.
33.5.1 Pending Request
In case multiple events occur in the same counter group, the sequence below is followed:
1. The lowest index event is given priority, and a corresponding delay is loaded into the counter.
2. The counter starts counting down. Other events remain pending.
3. The eMIOS/PIT flag is cleared for the event being serviced.
4. When the counter reaches zero, ADC conversion is triggered, provided that the previous
conversion (if any) is completed and arbitration grants the trigger to this counter.
5. The counter is loaded with the delay value corresponding to next pending flag and the sequence
follows. In case no more flags are pending, the counter resets.
The counters are also reset if the CTU halt bit (bit 9) in the SIU_HLT1 register is set.
33.5.2 Counter
The counters are 9-bit down-counters which are triggered by the logical OR output of the input events for
that counter group. A particular counter can only be triggered if some unmasked event is pending in that
counter group. As soon as a valid input event is detected, the current value register CTU_CVRm (i.e.,
counter) is loaded with the corresponding start value for that particular event and the counter starts
counting down. The start value for the particular event is based on the delay selection bits of the
corresponding CTU_EVTCFGR register. The counter stops automatically when the count value reaches
‘0’ and provides the ADC trigger and corresponding channel number, provided that it wins the arbitration
and the previous ADC conversion (if any) is over.
In case some flags are pending in the counter group and they are not masked, the counter is reloaded with
a delay value corresponding to the lowest index pending flag and starts counting down again. If no valid
flag is set for the counter group, the counter remains in reset state.
The counters are in the following states after each reset condition:
• System reset — Reset (all zeros)
• Power On Reset — Reset (all zeros)
• Wake-up from low power Sleep mode — Reset (all zeros)
33.5.3 Prescaler
The counter clock is the prescaler output. To offer a wide counting period range, the prescaler allows to
divide the clock by 2
0
to 2
10
depending on the prescaler configuration (PRESC_CONF) bits of the
CTU_CSR register.
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