NXP Semiconductors PXN2020 - 6.2.2 Register Descriptions; 6.2.2.1 Clock Source Register (CRP_CLKSRC)

Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 6-5
6.2.2 Register Descriptions
This section lists the CRP registers in address order and describes the registers and their bit fields.
6.2.2.1 Clock Source Register (CRP_CLKSRC)
The CRP_CLKSRC contains:
• Enable bits for the 32 kHz OSC, 128 kHz IRC, and 4 – 40 MHz OSC
• Low power configuration for the 4 – 40 MHz OSC
• The trim values for the 16 MHz IRC and 128 kHz IRC
0x0070 CRP_SOCSC—SoC status and control register R/W 0x4000_0000 6.2.2.12/6-15
0x0074–0x03FF Reserved
Offset: CRP_BASE + 0x0000 Access: User read/write
01234567891011 12 1314 15
R IRC
TRIM
EN
0 0 0 0
PREDIV
0 0 0 0
EN128K
IRC
EN32
KOSC
ENLP
OSC
EN40M
OSC
W
Reset
1
000000000000 0 00 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0
TRIM128IRC
0 0
TRIM16IRC
W
Reset
1
000111110011 1 11 1
1
These bits are only reset by power-on, VDD12 LVI, VDD33 LVI, VDDSYN LVI, VDD5 Low LVI, and VDD5 LVI.
Figure 6-2. Clock Source Register (CRP_CLKSRC)
Table 6-2. CRP_CLKSRC Field Descriptions
Field Description
IRCTRIMEN IRC Trim Enable. The IRCTRIMEN bit enable write access to TRIM128IRC and TRIM16IRC.
0 IRC trim bit writes disabled.
1 IRC trim bit writes enabled.
PREDIV RTC Clock Pre-divider. The PREDIV bits control the pre-divider for the RTC clock source. Divide clock
sources are the 32 kHz OSC, 128 kHz IRC, 16 MHz IRC, or the 4 – 40 MHz OSC. See the CLKSEL bitfield
in Tabl e 6 -3 .The pre-divider is in addition to any other divide selects internal to the RTC logic.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
Other Reserved
Table 6-1. CRP Memory Map (continued)
Offset from
CRP_BASE
(0xFFFE_C000)
Register Access Reset Value Section/Page