NXP Semiconductors PXN2020 - 13.3.2.1 Cache Organization

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-22 Freescale Semiconductor
match a valid cache tag entry (misses in the cache) or a write access must be written through to memory,
the cache performs a bus cycle on the system bus. Figure 13-13 shows a block diagram of the unified cache
in the e200z6.
Figure 13-13. e200z6 Unified Cache Block Diagram
13.3.2.1 Cache Organization
The e200z6 cache is organized as 4 or 8 ways of 128 sets with each line containing 32 bytes (four
doublewords) plus parity of storage. Figure 13-14 illustrates the cache organization, terminology used, the
cache line format, and cache tag formats.
Bus
Interface
Unit
Address/
Control
Cache
Control Logic
Tag Array
Data Array
Data Path
Processor
Core
Address Path
Control
Data
Address
Bus
Data
Control
Data
Memory
Unit
Address
System
Management