NXP Semiconductors PXN2020 - 13.2.3 e200 z6 Core Complex Features Not Supported in the Device; 13.3 Functional Description; 13.3.1 Memory Management Unit (MMU)

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-14 Freescale Semiconductor
13.2.3 e200z6 Core Complex Features Not Supported in the Device
The device implements a subset of the e200z6 core complex features. The e200z6 core complex features
that are not supported in the device are described in Table 13-2.
13.3 Functional Description
The following sections describe the functions of the e200z6 core blocks.
13.3.1 Memory Management Unit (MMU)
The memory management unit (MMU) is an implementation built on the Power Architecture embedded
category with a 32-entry fully associative translation lookaside buffer (TLB). The Power Architecture
embedded category divides the effective and real address space into pages. The page represents the
granularity of effective address translation, permission control, and memory/cache attributes. The e200z6
MMU supports the following nine page sizes: (4, 16, 64, and 256 KB, 1, 4, 16, 64, and 256 MB).
Table 13-2. e200z6 Features Not Supported in the Device Core
Function / Category Description
Disabled events The unconditional debug event (UDE) is not supported.
Power management e200z6 core halted state and stopped state are not supported.
Power management The following low-power modes are not supported:
Doze mode
Nap mode
Sleep mode
Time-base interrupt wake-up from low-power mode is not supported.
Power management Core wake up is not supported.
MSR[WE] bit in the machine state register is not supported.
The OCR[WKUP] bit in the e200z6 OnCE control register (OCR) has no effect.
Machine check The machine check input pin is not supported. HID0 [EMCP] has no effect, and MCSR[MCP]
always reads a negated value.
PVR value Least significant halfword of processor version register (PVR) is 0x 0000, that contains the
following bitfields:
MBG Use = 0x00
MBG Rev = 0x0
MBG ID = 0x0
The PVR register has two bitfields in the device.
Reservation management Reservation management logic external to the e200z6 is not implemented.
Verification The system version register (SVR) of the e200z6 is 0x 0000_0000.
Time base The decrement counters are always enabled in the e200z6.
Time Base The timer external clock is not connected to a clock; Do not select the timer external clock.
Context control The CTXCR and ALTCXTCR registers are not supported.