NXP Semiconductors PXN2020 - 32.4.1.1 START Signal

Inter-Integrated Circuit Bus Controller Module (I
2
C)
PXN20 Microcontroller Reference Manual, Rev. 1
32-12 Freescale Semiconductor
Figure 32-10. I
2
C Bus Transmission Signals
32.4.1.1 START Signal
When the bus is free, i.e.,no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in Figure 32-10, a
START signal is a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of
a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their
idle states.
Figure 32-11. Start and Stop conditions
SCL
SDA
Start
Signal
Ack
Bit
12345678
MSB LSB
12345678
MSB LSB
Stop
Signal
No
SCL
SDA
12345678
MSB LSB
12 5 678
MSB LSB
Repeated
34
9 9
AD0 AD1 AD2 AD3 AD4 AD5 AD6 R/W XXX D0 D1 D2 D3 D4 D5 D6 D7
Calling Address Read/ Data Byte
AD0 AD1 AD2 AD3 AD4 AD5 AD6 R/W AD0 AD1 AD2 AD3 AD4 AD5 AD6 R/W
New Calling Address
99
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address Read/
Write
Stop
Signal
No
Ack
Bit
Read/
Write
SDA
SCL
START condition STOP condition