Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-15
24.3.2.6 eDMA Clear Enable Request Register (EDMA_CERQR)
The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_ERQRL to disable the eDMA request for a given channel. The data value on a register write
causes the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1 (CERQ[0]) provides a
global clear function, forcing the entire contents of the EDMA_ERQRL to be zeroed, disabling all eDMA
request inputs. Reads of this register return all zeroes.
If bit 0 is set, the CERQ command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
24.3.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
The EDMA_SEEIR provides a memory-mapped mechanism to set a given bit in the EDMA_EEIRL to
enable the error interrupt for a given channel. The data value on a register write causes the corresponding
Table 24-7. EDMA_SERQR Field Descriptions
Field Descriptions
NOP No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
SERQ[0:6] Set Enable Request.
0–31 Set corresponding bit in EDMA_ERQRL.
32–63 Reserved.
64–127 Set all bits in EDMA_ERQRL.
Note: Bits 2 and 3(SERQR[1:2]) are not used.
Offset: EDMA_BASE + 0x0019 Access: User write-only
01234567
R
W NOP CERQ[0:6]
Reset00000000
Figure 24-7. eDMA Clear Enable Request Register (EDMA_CERQR)
Table 24-8. EDMA_CERQR Field Descriptions
Field Description
NOP No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
CERQ[0:6] Clear Enable Request.
0–31 Clear corresponding bit in EDMA_ERQRL.
32–63 Reserved.
64–127 Clear all bits in EDMA_ERQRL.
Note: Bits 2 and 3 (CERQR[1:2]) are not used.
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