NXP Semiconductors PXN2020 - 30.3.2 Register Descriptions; 30.3.2.1 DSPI Module Configuration Register (DSPI_MCR)

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-7
30.3.2 Register Descriptions
This section lists the DSPI registers in address order and describes the registers and their bit fields.
30.3.2.1 DSPI Module Configuration Register (DSPI_MCR)
The DSPI_MCR contains bits that configure various attributes associated with DSPI operation. The HALT
and MDIS bits can be changed at any time but only takes effect on the next frame boundary. Only the
HALT and MDIS bits in the DSPI_MCR may be changed while the DSPI is in the Running state.
0x00D0 DSPI_DSICR1—DSPI DSI TSB configuration register 1 R/W 0x0000_0000 30.3.2.15/30-27
0x00D4–0x3FFF Reserved
Offset: DSPI_BASE + 0x0000 Access: User read/write
0 1 23456789101112131415
R
MSTR
CONT_
SCKE
DCONF FRZ MTFE
PCS
SE
ROOE
00
PCS
IS5
PCS
IS4
PCS
IS3
PCS
IS2
PCS
IS1
PCS
IS0
W
Reset0 0 00000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
MDIS
DIS_
TXF
DIS_
RXF
CLR_
TXF
CLR_
RXF
SMPL_PT
0000000
HALT
W
Reset0 1 00000000000001
Figure 30-3. DSPI Module Configuration Register (DSPI_MCR)
Table 30-3. DSPI_MCR Field Descriptions
Field Description
MSTR Master/Slave Mode Select. The MSTR bit configures the DSPI for either Master Mode or Slave Mode.
0 DSPI is in Slave Mode.
1 DSPI is in Master Mode.
CONT_SCKE Continuous SCK Enable. The CONT_SCKE bit enables the Serial Communication Clock (SCK) to run
continuously. See Section 30.4.9, Continuous Serial Communications Clock, for details.
0 Continuous SCK disabled.
1 Continuous SCK enabled.
Table 30-2. DSPI Memory Map (continued)
Offset from
DSPI_BASE
DSPI_A = 0xFFF9_0000
DSPI_B = 0xFFF9_4000
DSPI_C = 0xC3F9_0000
DSPI_D = 0xC3F9_4000
Register Access Reset Value Section/Page