Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-44 Freescale Semiconductor
The delay between the assertion of the PCSx signals and the assertion of PCSS is selected by the PCSSCK
field in the DSPI_CTARn register based on the following formula:
Eqn. 30-8
At the end of the transfer the delay between PCSS negation and PCSx negation is selected by the PASC
field in the DSPI_CTARn register based on the following formula:
Eqn. 30-9
Table 30-31 shows an example of the computed t
PCSSCK
delay.
Table 30-32 shows an example of the computed the t
PASC
delay.
The PCSS signal is not supported when Continuous Serial Communication SCK is enabled
(CONT_SCKE = 1).
30.4.8 Transfer Formats
The SPI serial communication is controlled by the serial communications clock (SCK) signal and the PCS
signals. The SCK signal provided by the master device synchronizes shifting and sampling of the data on
the SIN and SOUT pins. The PCS signals serve as enable signals for the slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes
registers (DSPI_CTARn) select the polarity and phase of the serial clock, SCK. The polarity bit selects the
idle state of the SCK. The clock phase bit selects if the data on SOUT is valid before or on the first SCK
edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DSPI_CTAR0 (SPI) or DSPI_CTAR1 (DSI)
select the polarity and phase of the serial clock. Even though the bus Slave does not control the SCK signal,
clock polarity, clock phase and number of bits to transfer must be identical for the master device and the
slave device to ensure proper transmission.
Table 30-31. Peripheral Chip Select Strobe Assert Computation Example
PCSSCK Prescaler
f
SYS Delay before Transfer
0b11 7 100 MHz 70.0 ns
Table 30-32. Peripheral Chip Select Strobe Negate Computation Example
PASC Prescaler
f
SYS Delay after Transfer
0b11 7 100 MHz 70.0 ns
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