NXP Semiconductors PXN2020 - 35.5.2 e200 z0 OnCE Controller Functional Description; 35.5.2.1 Enabling the TAP Controller; 35.5.3 e200 z0 OnCE Controller Register Descriptions; 35.5.3.1 OnCE Command Register (OCMD)

IEEE 1149.1 Test Access Port Controller (JTAGC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 35-13
Figure 35-7. e200z0 OnCE Block Diagram
35.5.2 e200z0 OnCE Controller Functional Description
The functional description for the e200z0 OnCE controller is the same as for the JTAGC, with the
differences described below.
35.5.2.1 Enabling the TAP Controller
To access the e200z0 OnCE controller, the proper JTAGC instruction needs to be loaded in the JTAGC
instruction register, as discussed in Section 35.1.3.4, TAP Sharing Mode. The e200z0 OnCE TAP
controller may either be accessed independently or chained with the e200z6 OnCE TAP controller, such
that the TDO output of the e200z6 TAP controller is fed into the TDI input of the e200z0 TAP controller.
The chained configuration allows commands to be loaded into both core’s OnCE registers in one shift
operation, so that both cores can be sent a GO command at the same time for example.
35.5.3 e200z0 OnCE Controller Register Descriptions
Most e200z0 OnCE debug registers are fully documented in the e200z0 Reference Manual.
35.5.3.1 OnCE Command Register (OCMD)
The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data from the TDI
pin and serves as the instruction register (IR). It holds the 10-bit commands to be used as input for the
e200z0 OnCE Decoder. The OCMD is shown in Figure 35-8. The OCMD is updated when the TAP
TCK
e200z0_TMS
TDI
Test Access Port (TAP)
e200z0_TDO
Bypass Register
External Data Register
Controller
TAP Instruction Register
OnCE Mapped Debug Registers
Auxiliary Data Register
e200z0_TRST
(OnCE OCMD)
TDO Mux
Control
{
From
JTAGC
(to JTAGC)